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DFT
2007
IEEE
123views VLSI» more  DFT 2007»
15 years 9 months ago
Checker Design for On-line Testing of Xilinx FPGA Communication Protocols
In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemen...
Martin Straka, Jiri Tobola, Zdenek Kotásek
ICC
2007
IEEE
140views Communications» more  ICC 2007»
15 years 9 months ago
Performance Analysis of Full-rate STBCs from Coordinate Interleaved Orthogonal Designs
— In this paper, we derive the theoretical symbol error rate (SER) for a full-rate space-time block coded (STBCed) system with coordinate interleaved orthogonal designs (CIODs) o...
Ying Rao Wei, M. Z. Wang
120
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ISCAS
2006
IEEE
113views Hardware» more  ISCAS 2006»
15 years 9 months ago
Low power state-parallel relaxed adaptive Viterbi decoder design and implementation
Abstract— In this paper, we present an algorithm/architecturelevel design solution for implementing state-parallel adaptive Viterbi decoders that, compared with their Viterbi cou...
Fei Sun, Tong Zhang
IWPC
2003
IEEE
15 years 8 months ago
Automatic Design Pattern Detection
We detect design patterns in legacy code combining static and dynamic analyses. The analyses do not depend on coding or naming conventions. We classify potential pattern instances...
Dirk Heuzeroth, Thomas Holl, Gustav Högstr&ou...
CODES
2000
IEEE
15 years 7 months ago
Linking codesign and reuse in embedded systems design
This paper presents a complete codesign environment for embedded systems which combines automatic partitioning with reuse from a module database. Special emphasis has been put on ...
Matthias Meerwein, C. Baumgartner, W. Glauert