7189 search results - page 371 / 1438 » Connecting Design with Code |
182
Voted
SOCC
2008
IEEE
15 years 11 months ago
2008
IEEE
Abstract— In this paper we present an efficient system-onchip implementation of a 1-Gbps LDPC decoder for 4G (or beyond 3G) wireless standards. The decoder has a scalable datapa...
117
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COMSWARE
2007
IEEE
15 years 11 months ago
2007
IEEE
— Sequence design and resource allocation for a symbol-asynchronous chip-synchronous code division multiple access (CDMA) system is considered in this paper. A simple lower bound...
113
Voted
DATE
2007
IEEE
15 years 11 months ago
2007
IEEE
Non-volatile Flash memories are becoming more and more popular in Systems-on-Chip (SoC). Embedded Flash (eFlash) memories are based on the well-known floatinggate transistor conce...
149
Voted
IPPS
2007
IEEE
15 years 11 months ago
2007
IEEE
Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used f...
125
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ITNG
2007
IEEE
15 years 11 months ago
2007
IEEE
The Super Iterator pattern, like the standard Iterator pattern, traverses an unknown data structure without exposing that structure. With the standard Iterator pattern, clients mu...