7189 search results - page 517 / 1438 » Connecting Design with Code |
196
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DFT
2008
IEEE
16 years 1 months ago
2008
IEEE
The paper presents a new technique for designing a concurrently checking combinational circuit. The technique is based on partitioning the circuit into two independent sub-circuit...
178
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SIPS
2008
IEEE
16 years 1 months ago
2008
IEEE
This paper presents a low-complexity, high-speed 4-dimensional 8-ary Phase Shift Keying Trellis Coded Modulation (4-D 8PSK TCM) decoder. In the design, an efficient architecture f...
171
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ICMCS
2005
IEEE
16 years 23 days ago
2005
IEEE
The paper presents a high-performance architecture of the bit-plane coder for the embedded block coding algorithm in JPEG 2000. The architecture adopts a pipeline structure and is...
204
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EUROPAR
2004
Springer
16 years 17 days ago
2004
Springer
We present hoc: a fast, scalable object repository providing programmers with a general storage module. hoc may be used to implement DSMs as well as distributed cache subsystems. h...
224
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PPSN
2004
Springer
16 years 16 days ago
2004
Springer
Abstract. A key problem in designing artificial neural networks for visual object recognition tasks is the proper choice of the network architecture. Evolutionary optimization met...