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» Constraint Analysis for DSP Code Generation
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DAC
1995
ACM
15 years 8 months ago
A Transformation-Based Approach for Storage Optimization
High-level synthesis (HLS) has been successfully targeted towards the digital signal processing (DSP) domain. Both application-speci c integrated circuits (ASICs) and application-...
Wei-Kai Cheng, Youn-Long Lin
RTCSA
2006
IEEE
15 years 11 months ago
Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors
To support high-performance and low-power for multimedia applications and for hand-held devices, embedded VLIW DSP processors are of research focus. With the tight resource constr...
Chi Wu, Kun-Yuan Hsieh, Yung-Chia Lin, Chung-Ju Wu...
DAC
1996
ACM
15 years 9 months ago
Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures
In this paper we address the problem of code generation for basic blocks in heterogeneous memory-register DSP processors. We propose a new a technique, based on register-transfer ...
Guido Araujo, Sharad Malik, Mike Tien-Chien Lee
LCPC
2005
Springer
15 years 10 months ago
Compiler Supports and Optimizations for PAC VLIW DSP Processors
Abstract. Compiler is substantially regarded as the most essential component in the software toolchain to promote a successful processor design. This paper describes our preliminar...
Yung-Chia Lin, Chung-Lin Tang, Chung-Ju Wu, Ming-Y...
CODES
2001
IEEE
15 years 8 months ago
System canvas: a new design environment for embedded DSP and telecommunication systems
We present a new design environment, called System Canvas, targeted at DSP and telecommunication system designs. Our environment uses an easy-to-use block-diagram syntax to specif...
Praveen K. Murthy, Etan G. Cohen, Steve Rowland