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ISPD
2010
ACM
217views Hardware» more  ISPD 2010»
15 years 8 months ago
ITOP: integrating timing optimization within placement
Timing-driven placement is a critical step in nanometerscale physical synthesis. To improve design timing on a global scale, net-weight based global timing-driven placement is a c...
Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy,...
SAMOS
2007
Springer
15 years 8 months ago
An Evolutionary Approach to Area-Time Optimization of FPGA designs
—This paper presents a new methodology based on evolutionary multi-objective optimization (EMO) to synthesize multiple complex modules on programmable devices (FPGAs). It starts ...
Fabrizio Ferrandi, Pier Luca Lanzi, Gianluca Paler...
CASES
2004
ACM
15 years 7 months ago
High-level power analysis for on-chip networks
As on-chip networks become prevalent in multiprocessor systemson-a-chip and multi-core processors, they will be an integral part of the design flow of such systems. With power in...
Noel Eisley, Li-Shiuan Peh
CDC
2009
IEEE
156views Control Systems» more  CDC 2009»
15 years 6 months ago
The nullspace method - a unifying paradigm to fault detection
— The nullspace method is a powerful framework to solve the synthesis problem of fault detection filters in the most general setting. It is also well suited to address the least...
András Varga
ALT
1998
Springer
15 years 6 months ago
Synthesizing Learners Tolerating Computable Noisy Data
An index for an r.e. class of languages (by definition) generates a sequence of grammars defining the class. An index for an indexed family of recursive languages (by definition) ...
John Case, Sanjay Jain