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118
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MICRO
2009
IEEE
147views Hardware» more  MICRO 2009»
15 years 7 months ago
Complexity effective memory access scheduling for many-core accelerator architectures
Modern DRAM systems rely on memory controllers that employ out-of-order scheduling to maximize row access locality and bank-level parallelism, which in turn maximizes DRAM bandwid...
George L. Yuan, Ali Bakhoda, Tor M. Aamodt
199
Voted
OOPSLA
2009
Springer
15 years 7 months ago
Static extraction and conformance analysis of hierarchical runtime architectural structure using annotations
An object diagram makes explicit the object structures that are only implicit in a class diagram. An object diagram may be missing and must extracted from the code. Alternatively,...
Marwan Abi-Antoun, Jonathan Aldrich
115
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SIGMETRICS
2009
ACM
165views Hardware» more  SIGMETRICS 2009»
15 years 7 months ago
Understanding intrinsic characteristics and system implications of flash memory based solid state drives
Flash Memory based Solid State Drive (SSD) has been called a “pivotal technology” that could revolutionize data storage systems. Since SSD shares a common interface with the t...
Feng Chen, David A. Koufaty, Xiaodong Zhang
105
Voted
HOST
2008
IEEE
15 years 7 months ago
Place-and-Route Impact on the Security of DPL Designs in FPGAs
—Straightforward implementations of cryptographic algorithms are known to be vulnerable to attacks aimed not at the mathematical structure of the cipher but rather at the weak po...
Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Dange...
GLVLSI
2006
IEEE
152views VLSI» more  GLVLSI 2006»
15 years 6 months ago
2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology
This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as c...
Rashed Zafar Bhatti, Monty Denneau, Jeff Draper