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POPL
2007
ACM
16 years 1 months ago
Dynamic heap type inference for program understanding and debugging
C programs can be difficult to debug due to lax type enforcement and low-level access to memory. We present a dynamic analysis for C that checks heap snapshots for consistency wit...
Ben Liblit, Chloë W. Schulze, Marina Polishch...
DAC
2004
ACM
16 years 2 months ago
Dynamic FPGA routing for just-in-time FPGA compilation
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
RSP
2005
IEEE
15 years 7 months ago
Test-Time, Run-Time, and Simulation-Time Temporal Assertions in RSP
For cost-effective prototyping, system designers should have a clear understanding of the intended use of the prototype under development. This paper describes a classification of...
Doron Drusinsky, Man-tak Shing, Kadir Alpaslan Dem...
CORR
2010
Springer
155views Education» more  CORR 2010»
14 years 12 months ago
A QoS Provisioning Recurrent Neural Network based Call Admission Control for beyond 3G Networks
The Call admission control (CAC) is one of the Radio Resource Management (RRM) techniques that plays influential role in ensuring the desired Quality of Service (QoS) to the users...
H. S. Ramesh Babu, Gowrishankar, P. S. Satyanaraya...
ISCA
2012
IEEE
279views Hardware» more  ISCA 2012»
13 years 4 months ago
Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...
Rachata Ausavarungnirun, Kevin Kai-Wei Chang, Lava...