74 search results - page 6 / 15 » Controlling Peak Power During Scan Testing |
164
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EVOW
1999
Springer
15 years 6 months ago
1999
Springer
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...
103
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ITC
2003
IEEE
15 years 7 months ago
2003
IEEE
As semiconductor manufacturing technology advances, power dissipation and noise in scan testing has become a critical problem. In our studies on practical LSI manufacturing, we ha...
100
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ASPDAC
2006
ACM
15 years 7 months ago
2006
ACM
Abstract— For scan-based testing, the high test power consumption may cause test power management problems, and the extra scan chain connections may cause routability degradation...
100
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DAC
2007
ACM
16 years 2 months ago
2007
ACM
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
ISQED
2010
IEEE
15 years 6 months ago
2010
IEEE
— This paper proposes a two-dimensional scan shift control concept for multiple scan chain design. Multiple scan chain test scheme provides very low scan power by skipping many l...