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CODES
2007
IEEE
15 years 6 months ago
Performance and resource optimization of NoC router architecture for master and slave IP cores
System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper presents a parameterized ...
Glenn Leary, Krishna Mehta, Karam S. Chatha
ER
2007
Springer
190views Database» more  ER 2007»
15 years 6 months ago
The CIDOC Conceptual Reference Model - A New Standard for Knowledge Sharing
The tutorial first addresses requirements and semantic problems to integrate digital information into large scale, meaningful networks of knowledge that support not only access to...
Martin Doerr, Christian-Emil Ore, Stephen Stead
VLSID
2002
IEEE
98views VLSI» more  VLSID 2002»
16 years 7 days ago
On Test Scheduling for Core-Based SOCs
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
Sandeep Koranne
ISCA
2012
IEEE
244views Hardware» more  ISCA 2012»
13 years 2 months ago
Scheduling heterogeneous multi-cores through performance impact estimation (PIE)
Single-ISA heterogeneous multi-core processors are typically composed of small (e.g., in-order) power-efficient cores and big (e.g., out-of-order) high-performance cores. The eff...
Kenzo Van Craeynest, Aamer Jaleel, Lieven Eeckhout...
EDBT
2006
ACM
137views Database» more  EDBT 2006»
15 years 12 months ago
Data Mapping as Search
In this paper, we describe and situate the TUPELO system for data mapping in relational databases. Automating the discovery of mappings between structured data sources is a long st...
George H. L. Fletcher, Catharine M. Wyss