We propose a generic information-theoretic distinguisher for differential side-channel analysis. Our model of side-channel leakage is a refinement of the one given by Standaert et ...
Under a simple power leakage model based on Hamming weight, a software implementation of a data-whitening routine is shown to be vulnerable to a first-order Differential Power Anal...
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
Several dual-rail logic styles make use of single-rail flip-flops for storing intermediate states. We show that single mask bits, as applied by various side-channel resistant logic...
Amir Moradi, Thomas Eisenbarth, Axel Poschmann, Ch...
This paper proposes an efficient method to predict the worst case of voltage violation by multi-domain clock gating in a three-dimensional (3D) on-chip power network considering l...