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141
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ISCA
1993
IEEE
125views Hardware» more  ISCA 1993»
15 years 6 months ago
Evaluation of Mechanisms for Fine-Grained Parallel Programs in the J-Machine and the CM-5
er uses an abstract machine approach to compare the mechanisms of two parallel machines: the J-Machine and the CM-5. High-level parallel programs are translated by a single optimi...
Ellen Spertus, Seth Copen Goldstein, Klaus E. Scha...
146
Voted
CASES
2007
ACM
15 years 5 months ago
Fragment cache management for dynamic binary translators in embedded systems with scratchpad
Dynamic binary translation (DBT) has been used to achieve numerous goals (e.g., better performance) for general-purpose computers. Recently, DBT has also attracted attention for e...
José Baiocchi, Bruce R. Childers, Jack W. D...
FASE
2006
Springer
15 years 5 months ago
Trace-Based Memory Aliasing Across Program Versions
One of the major costs of software development is associated with testing and validation of successive versions of software systems. An important problem encountered in testing and...
Murali Krishna Ramanathan, Suresh Jagannathan, Ana...
INTERSENSE
2006
ACM
15 years 7 months ago
Programming wireless sensor networks with logical neighborhoods
— Wireless sensor network (WSN) architectures often feature a (single) base station in charge of coordinating the application functionality. Although this assumption simplified ...
Luca Mottola, Gian Pietro Picco
126
Voted
IPPS
2007
IEEE
15 years 8 months ago
A Heterogeneous Lightweight Multithreaded Architecture
Programs with irregular patterns of dynamic data structures and/or those with complicated control structures such as recursion are notoriously difficult to parallelize efficient...
Sheng Li, Amit Kashyap, Shannon K. Kuntz, Jay B. B...