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» Crosstalk analysis in nanometer technologies
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CODES
2004
IEEE
15 years 1 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan
DAC
2003
ACM
15 years 10 months ago
Multilevel global placement with retiming
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous designs, this requires retiming and pipel...
Jason Cong, Xin Yuan
ICCAD
2007
IEEE
108views Hardware» more  ICCAD 2007»
15 years 6 months ago
Novel wire density driven full-chip routing for CMP variation control
— As nanometer technology advances, the post-CMP dielectric thickness variation control becomes crucial for manufacturing closure. To improve CMP quality, dummy feature filling ...
Huang-Yu Chen, Szu-Jui Chou, Sheng-Lung Wang, Yao-...
DATE
2006
IEEE
115views Hardware» more  DATE 2006»
15 years 3 months ago
Optimal periodic testing of intermittent faults in embedded pipelined processor applications
Today’s nanometer technology trends have a very negative impact on the reliability of semiconductor products. Intermittent faults constitute the largest part of reliability fail...
Nektarios Kranitis, Andreas Merentitis, N. Laoutar...
ASPDAC
2007
ACM
133views Hardware» more  ASPDAC 2007»
15 years 1 months ago
Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM
- For sub-90nm technology nodes and below, random fluctuations of within-die physical process properties are also known as random on-chip variation (OCV). It impacts on the VLSI/So...
Jun-Fu Huang, Victor C. Y. Chang, Sally Liu, Kelvi...