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85
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DAC
2008
ACM
15 years 10 months ago
Latency and bandwidth efficient communication through system customization for embedded multiprocessors
We present a cross-layer customization methodology for latency and bandwidth efficient inter-core communication in embedded multiprocessors. The methodology integrates compiler, o...
Chenjie Yu, Peter Petrov
86
Voted
FPL
2007
Springer
146views Hardware» more  FPL 2007»
15 years 3 months ago
Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips
The complexity of today’s embedded applications requires modern high-performance embedded System-on-Chip (SoC) platforms to be multiprocessor architectures. Advances in FPGA tec...
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere
EMSOFT
2005
Springer
15 years 3 months ago
Optimizing inter-processor data locality on embedded chip multiprocessors
Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. T...
Guilin Chen, Mahmut T. Kandemir
CASES
2006
ACM
15 years 3 months ago
Integrated scratchpad memory optimization and task scheduling for MPSoC architectures
Multiprocessor system-on-chip (MPSoC) is an integrated circuit containing multiple instruction-set processors on a single chip that implements most of the functionality of a compl...
Vivy Suhendra, Chandrashekar Raghavan, Tulika Mitr...
DFT
1999
IEEE
114views VLSI» more  DFT 1999»
15 years 1 months ago
Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM
A programmable single-chip multiprocessor system for video coding has been developed. The system is implemented in a high-performance 0.25 m logic/embedded DRAM process. It integr...
Markus Rudack, Dirk Niggemeyer