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» DNS performance and the effectiveness of caching
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88
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MICRO
1999
IEEE
98views Hardware» more  MICRO 1999»
15 years 4 months ago
Instruction Fetch Mechanisms for Multipath Execution Processors
Branch mispredictions can have a major performance impact on high-performance processors. Multipath execution has recently been introduced to help limit the misprediction penaltie...
Artur Klauser, Dirk Grunwald
96
Voted
MICRO
1997
IEEE
90views Hardware» more  MICRO 1997»
15 years 4 months ago
ProfileMe: Hardware Support for Instruction-Level Profiling on Out-of-Order Processors
Profile data is valuable for identifying performance bottlenecks and guiding optimizations. Periodic sampling of a processor's performance monitoring hardware is an effective...
Jeffrey Dean, James E. Hicks, Carl A. Waldspurger,...
IPPS
2007
IEEE
15 years 6 months ago
Leakage Energy Reduction in Value Predictors through Static Decay
As process technology advances toward deep submicron (below 90nm), static power becomes a new challenge to address for energy-efficient high performance processors, especially for...
Juan M. Cebrian, Juan L. Aragón, José...
100
Voted
CODES
1998
IEEE
15 years 4 months ago
Software timing analysis using HW/SW cosimulation and instruction set simulator
Timing analysis for checking satisfaction of constraints is a crucial problem in real-time system design. In some current approaches, the delay of software modules is precalculate...
Jie Liu, Marcello Lajolo, Alberto L. Sangiovanni-V...
JPDC
2010
106views more  JPDC 2010»
14 years 11 months ago
Feedback-directed page placement for ccNUMA via hardware-generated memory traces
Non-uniform memory architectures with cache coherence (ccNUMA) are becoming increasingly common, not just for large-scale high performance platforms but also in the context of mul...
Jaydeep Marathe, Vivek Thakkar, Frank Mueller