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HPCA
2012
IEEE
13 years 5 months ago
Staged Reads: Mitigating the impact of DRAM writes on DRAM reads
Main memory latencies have always been a concern for system performance. Given that reads are on the critical path for CPU progress, reads must be prioritized over writes. However...
Niladrish Chatterjee, Naveen Muralimanohar, Rajeev...
ICPPW
2006
IEEE
15 years 3 months ago
Parallel Algorithms for Motion Panorama Construction
A motion panorama is an efficient and compact representation of the underlying video. However, the motion panorama construction process is computationally intensive and hence extr...
Yong Wei, Hongyu Wang, Suchendra M. Bhandarkar, Ka...
CORR
2011
Springer
181views Education» more  CORR 2011»
14 years 1 months ago
Garbage Collection for Multicore NUMA Machines
Modern high-end machines feature multiple processor packages, each of which contains multiple independent cores and integrated memory controllers connected directly to dedicated p...
Sven Auhagen, Lars Bergstrom, Matthew Fluet, John ...
CPHYSICS
2010
135views more  CPHYSICS 2010»
14 years 10 months ago
An events based algorithm for distributing concurrent tasks on multi-core architectures
In this paper, a programming model is presented which enables scalable parallel performance on multi-core shared memory architectures. The model has been developed for application...
David W. Holmes, John R. Williams, Peter Tilke
EUROPAR
2007
Springer
15 years 4 months ago
Esodyp+: Prefetching in the Jackal Software DSM
Abstract. Prefetching transfers a data item in advance from its storage location to its usage location so that communication is hidden and does not delay computation. We present a ...
Michael Klemm, Jean Christophe Beyler, Ronny T. La...