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» Data Reduction Using Multiple Models Integration
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ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
15 years 10 months ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
130
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CLUSTER
2009
IEEE
15 years 10 months ago
Combining I/O operations for multiple array variables in parallel netCDF
—Parallel netCDF (PnetCDF) is a popular library used in many scientific applications to store scientific datasets. It provides high-performance parallel I/O while maintaining ...
Kui Gao, Wei-keng Liao, Alok N. Choudhary, Robert ...
153
Voted
BMCBI
2011
14 years 10 months ago
Learning genetic epistasis using Bayesian network scoring criteria
Background: Gene-gene epistatic interactions likely play an important role in the genetic basis of many common diseases. Recently, machine-learning and data mining methods have be...
Xia Jiang, Richard E. Neapolitan, M. Michael Barma...
156
Voted
PVLDB
2010
175views more  PVLDB 2010»
15 years 1 months ago
Dynamic Join Optimization in Multi-Hop Wireless Sensor Networks
To enable smart environments and self-tuning data centers, we are developing the Aspen system for integrating physical sensor data, as well as stream data coming from machine logi...
Svilen R. Mihaylov, Marie Jacob, Zachary G. Ives, ...
DAC
1996
ACM
15 years 7 months ago
Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools
This paper provides a case study that shows how a demanding application stresses the capabilities of today's CAD tools, especially in the integration of products from multipl...
Stephen Dean Brown, Naraig Manjikian, Zvonko G. Vr...