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» Data Reduction Using Multiple Models Integration
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94
Voted
DAC
2004
ACM
15 years 10 months ago
FPGA power reduction using configurable dual-Vdd
Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a sat...
Fei Li, Yan Lin, Lei He
81
Voted
DAC
2002
ACM
15 years 10 months ago
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique
Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power diss...
Mohab Anis, Mohamed Mahmoud, Mohamed I. Elmasry, S...
CCE
2007
14 years 9 months ago
Control of integrated process networks - A multi-time scale perspective
In this paper, we analyze the dynamics of integrated process networks featuring large recycle streams and small purge streams. We consider a prototype network comprising of a reac...
Michael Baldea, Prodromos Daoutidis
ICCAD
2006
IEEE
165views Hardware» more  ICCAD 2006»
15 years 6 months ago
A fast block structure preserving model order reduction for inverse inductance circuits
Most existing RCL−1 circuit reductions stamp inverse inductance L−1 elements by a second-order nodal analysis (NA). The NA formulation uses nodal voltage variables and describ...
Hao Yu, Yiyu Shi, Lei He, David Smart
CDC
2009
IEEE
114views Control Systems» more  CDC 2009»
15 years 1 months ago
Parametric model order reduction accelerated by subspace recycling
Abstract-- Many model order reduction methods for parameterized systems need to construct a projection matrix V which requires computing several moment matrices of the parameterize...
Lihong Feng, Peter Benner, Jan G. Korvink