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MICRO
2007
IEEE
115views Hardware» more  MICRO 2007»
15 years 11 months ago
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...
Naveen Muralimanohar, Rajeev Balasubramonian, Norm...
FPGA
2007
ACM
163views FPGA» more  FPGA 2007»
15 years 11 months ago
Improved SAT-based Boolean matching using implicants for LUT-based FPGAs
Boolean matching (BM) is a widely used technique in FPGA resynthesis and architecture evaluation. In this paper we present several improvements to the recently proposed SAT-based ...
Jason Cong, Kirill Minkovich
152
Voted
SBACPAD
2006
IEEE
147views Hardware» more  SBACPAD 2006»
15 years 11 months ago
Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors
Neural-inspired branch predictors achieve very low branch misprediction rates. However, previously proposed implementations have a variety of characteristics that make them challe...
Daniel A. Jiménez, Gabriel H. Loh
144
Voted
IPPS
2005
IEEE
15 years 10 months ago
Performance Implications of Periodic Checkpointing on Large-Scale Cluster Systems
Large-scale systems like BlueGene/L are susceptible to a number of software and hardware failures that can affect system performance. Periodic application checkpointing is a commo...
Adam J. Oliner, Ramendra K. Sahoo, José E. ...
177
Voted
VEE
2005
ACM
119views Virtualization» more  VEE 2005»
15 years 10 months ago
A programmable microkernel for real-time systems
We present a new software system architecture for the implementation of hard real-time applications. The core of the system is a microkernel whose reactivity (interrupt handling a...
Christoph M. Kirsch, Marco A. A. Sanvido, Thomas A...