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» Datapath Scheduling using Dynamic Frequency Clocking
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IPPS
2005
IEEE
15 years 3 months ago
Dynamic Delay-Fault Injection for Reconfigurable Hardware
Modern internet and telephone switches consist of numerous VLSI-circuits operating at high frequencies to handle high bandwidths. It is beyond question that such systems must cont...
Bernhard Fechner
FPT
2005
IEEE
131views Hardware» more  FPT 2005»
15 years 3 months ago
Dynamic Voltage Scaling for Commercial FPGAs
A methodology for supporting dynamic voltage scaling (DVS) on commercial FPGAs is described. A logic delay measurement circuit (LDMC) is used to determine the speed of an inverter...
C. T. Chow, L. S. M. Tsui, Philip Heng Wai Leong, ...
EMSOFT
2004
Springer
15 years 2 months ago
Using resource reservation techniques for power-aware scheduling
Minimizing energy consumption is an important issue in the design of real-time embedded systems. As many embedded systems are powered by rechargeable batteries, the goal is to ext...
Claudio Scordino, Giuseppe Lipari
ANCS
2008
ACM
14 years 11 months ago
Low power architecture for high speed packet classification
Today's routers need to perform packet classification at wire speed in order to provide critical services such as traffic billing, priority routing and blocking unwanted Inte...
Alan Kennedy, Xiaojun Wang, Zhen Liu, Bin Liu
MAM
2007
157views more  MAM 2007»
14 years 9 months ago
Executing large algorithms on low-capacity FPGAs using flowpath partitioning and runtime reconfiguration
This paper describes a new method of executing a software program on an FPGA for embedded systems. Rather than combine reconfigurable logic with a microprocessor core, this method...
Darrin M. Hanna, Michael DuChene