72 search results - page 6 / 15 » Decision diagrams for linear arithmetic |
DATE
2003
IEEE
15 years 5 months ago
2003
IEEE
A new method is presented to model symbolically strongly nonlinear circuits, characterized by Piece-Wise Linear (PWL) functions. The method follows the idea of Bokhoven and Leenae...
105
Voted
VLSID
2002
IEEE
16 years 1 days ago
2002
IEEE
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
RTA
2010
Springer
15 years 3 months ago
2010
Springer
Decreasing diagrams technique (van Oostrom, 1994) is a technique that can be widely applied to prove confluence of rewrite systems. To directly apply the decreasing diagrams techn...
UAI
2008
15 years 1 months ago
2008
Decision circuits have been developed to perform efficient evaluation of influence diagrams [Bhattacharjya and Shachter, 2007], building on the advances in arithmetic circuits for...
DAC
1996
ACM
15 years 3 months ago
1996
ACM
Abstract-- It is impractical to verify multiplier or divider circuits entirely at the bit-level using ordered Binary Decision Diagrams (BDDs), because the BDD representations for t...