138 search results - page 20 / 28 » Delay modeling and static timing analysis for MTCMOS circuit... |
ITC
1998
IEEE
15 years 3 months ago
1998
IEEE
This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital c...
89
Voted
DAC
1999
ACM
15 years 4 months ago
1999
ACM
As interconnect feature sizes continue to scale to smaller dimensions, long interconnect can dominate the IC timing performance, but the interconnect parameter variations make it ...
108
Voted
TVLSI
2008
14 years 11 months ago
2008
This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding program...
DAC
2000
ACM
16 years 18 days ago
2000
ACM
We revisit a basic element of modern signal integrity analysis, the modeling of worst-case coupling capacitance effects within a switch factor (SF) based methodology. We show that...
RTCSA
1999
IEEE
15 years 3 months ago
1999
IEEE
Abstract. We present an approach to static priority preemptive process scheduling for the synthesis of hard realtime distributed embedded systems where communication plays an impor...