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CODES
2007
IEEE
15 years 8 months ago
Performance modeling for early analysis of multi-core systems
Performance analysis of microprocessors is a critical step in defining the microarchitecture, prior to register-transfer-level (RTL) design. In complex chip multiprocessor systems...
Reinaldo A. Bergamaschi, Indira Nair, Gero Dittman...
IJCNN
2000
IEEE
15 years 5 months ago
Pose Classification Using Support Vector Machines
The field of human-computer interaction has been widely investigated in the last years, resulting in a variety of systems used in different application fields like virtual reality...
Edoardo Ardizzone, Antonio Chella, Roberto Pirrone
ASPLOS
2009
ACM
16 years 2 months ago
Capo: a software-hardware interface for practical deterministic multiprocessor replay
While deterministic replay of parallel programs is a powerful technique, current proposals have shortcomings. Specifically, software-based replay systems have high overheads on mu...
Pablo Montesinos, Matthew Hicks, Samuel T. King, J...
IPPS
2007
IEEE
15 years 8 months ago
Design Alternatives for a High-Performance Self-Securing Ethernet Network Interface
This paper presents and evaluates a strategy for integrating the Snort network intrusion detection system into a high-performance programmable Ethernet network interface card (NIC...
Derek L. Schuff, Vijay S. Pai
ISCA
2006
IEEE
125views Hardware» more  ISCA 2006»
15 years 8 months ago
Architectural Semantics for Practical Transactional Memory
Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional stat...
Austen McDonald, JaeWoong Chung, Brian D. Carlstro...