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CODES
2006
IEEE
15 years 9 months ago
Creation and utilization of a virtual platform for embedded software optimization: : an industrial case study
Virtual platform (ViP), or ESL (Electronic System Level) simulation model, is one of the most widely renowned system level design techniques. In this paper, we present a case stud...
Sungpack Hong, Sungjoo Yoo, Sheayun Lee, Sangwoo L...
ISORC
2009
IEEE
15 years 9 months ago
Marte CCSL to Execute East-ADL Timing Requirements
In the automotive domain, several loosely-coupled Architecture Description Languages (ADLs) compete to proet of abstract modeling and analysis services on top of the implementatio...
Frédéric Mallet, Marie-Agnès ...
EMSOFT
2006
Springer
15 years 6 months ago
Modeling a system controller for timing analysis
Upper bounds on worst-case execution times, which are commonly called WCET, are a prerequisite for validating the temporal correctness of tasks in a real-time system. Due to the e...
Stephan Thesing
LCPC
2000
Springer
15 years 6 months ago
Improving Offset Assignment for Embedded Processors
Embedded systems consisting of the application program ROM, RAM, the embedded processor core, and any custom hardware on a single wafer are becoming increasingly common in applicat...
Sunil Atri, J. Ramanujam, Mahmut T. Kandemir
ISMVL
2007
IEEE
104views Hardware» more  ISMVL 2007»
15 years 9 months ago
Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL
Designing modern circuits comprised of millions of gates is a very challenging task. Therefore new directions are investigated for efficient modeling and verification of such syst...
Mahsan Amoui, Daniel Große, Mitchell A. Thor...