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» Design, Implementation and Performance Evaluation of IP-VPN
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FCCM
2003
IEEE
148views VLSI» more  FCCM 2003»
15 years 4 months ago
A Hardware Gaussian Noise Generator for Channel Code Evaluation
Hardware simulation of channel codes offers the potential of improving code evaluation speed by orders of magnitude over workstation- or PC-based simulation. We describe a hardwar...
Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y...
ER
2001
Springer
136views Database» more  ER 2001»
15 years 3 months ago
A Randomized Approach for the Incremental Design of an Evolving Data Warehouse
A Data Warehouse (DW) can be used to integrate data from multiple distributed data sources. A DW can be seen as a set of materialized views that determine its schema and its conten...
Dimitri Theodoratos, Theodore Dalamagas, Alkis Sim...
FCCM
2011
IEEE
241views VLSI» more  FCCM 2011»
14 years 3 months ago
Multilevel Granularity Parallelism Synthesis on FPGAs
— Recent progress in High-Level Synthesis (HLS) es has helped raise the abstraction level of FPGA programming. However implementation and performance evaluation of the HLS-genera...
Alexandros Papakonstantinou, Yun Liang, John A. St...
VLDB
2004
ACM
102views Database» more  VLDB 2004»
15 years 4 months ago
PIVOT and UNPIVOT: Optimization and Execution Strategies in an RDBMS
PIVOT and UNPIVOT, two operators on tabular data that exchange rows and columns, enable data transformations useful in data modeling, data analysis, and data presentation. They ca...
Conor Cunningham, Goetz Graefe, César A. Ga...
ISSS
2002
IEEE
141views Hardware» more  ISSS 2002»
15 years 4 months ago
An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems
Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and r...
Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin