497 search results - page 28 / 100 » Design Challenges for High Performance Nano-Technology |
DEBU
2006
14 years 9 months ago
2006
Performance tuning in modern database systems requires a lot of expertise, is very time consuming and often misdirected. Tuning attempts often lack a methodology that has a holist...
DAC
2003
ACM
15 years 10 months ago
2003
ACM
Parameter variation in scaled technologies beyond 90nm will pose a major challenge for design of future high performance microprocessors. In this paper, we discuss process, voltag...
TCOM
2008
14 years 9 months ago
2008
Abstract--This paper addresses the problem of joint optimization of transmit beamforming and space-frequency (SF) coding for MIMO-OFDM systems with spatial correlation feedback in ...
GLVLSI
2010
IEEE
15 years 2 months ago
2010
IEEE
Graphene nanoribbon tunneling FETs (GNR TFETs) are promising devices for post-CMOS low-power applications because of the low subthreshold swing, high Ion/Ioff, and potential for l...
96
Voted
CISIS
2009
IEEE
2009
IEEE
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints
15 years 4 months ago
—Regular multi-core processors are appearing in the embedded system market as high performance software programmable solutions. The use of regular interconnect fabrics for them a...