Sciweavers

497 search results - page 92 / 100
» Design Challenges for High Performance Nano-Technology
Sort
View
VEE
2009
ACM
171views Virtualization» more  VEE 2009»
15 years 4 months ago
Dynamic memory balancing for virtual machines
Virtualization essentially enables multiple operating systems and applications to run on one physical computer by multiplexing hardware resources. A key motivation for applying vi...
Weiming Zhao, Zhenlin Wang
DSD
2002
IEEE
96views Hardware» more  DSD 2002»
15 years 2 months ago
Networks on Silicon: Blessing or Nightmare?
Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow interconnect, power dissipation and distribution, and signal integrity. Those ...
Paul Wielage, Kees G. W. Goossens
CCR
2005
103views more  CCR 2005»
14 years 9 months ago
Part III: routers with very small buffers
Internet routers require buffers to hold packets during times of congestion. The buffers need to be fast, and so ideally they should be small enough to use fast memory technologie...
Mihaela Enachescu, Yashar Ganjali, Ashish Goel, Ni...
MICRO
2008
IEEE
139views Hardware» more  MICRO 2008»
15 years 3 months ago
Adaptive data compression for high-performance low-power on-chip networks
With the recent design shift towards increasing the number of processing elements in a chip, high-bandwidth support in on-chip interconnect is essential for low-latency communicat...
Yuho Jin, Ki Hwan Yum, Eun Jung Kim
MOBIQUITOUS
2007
IEEE
15 years 3 months ago
Minimum Disruption Service Composition and Recovery over Mobile Ad Hoc Networks
— The dynamic nature of mobile ad hoc networks poses fundamental challenges to the design of service composition schemes that can minimize the effect of service disruptions. Alth...
Shanshan Jiang, Yuan Xue, Douglas C. Schmidt