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MICRO
2009
IEEE
147views Hardware» more  MICRO 2009»
15 years 8 months ago
Complexity effective memory access scheduling for many-core accelerator architectures
Modern DRAM systems rely on memory controllers that employ out-of-order scheduling to maximize row access locality and bank-level parallelism, which in turn maximizes DRAM bandwid...
George L. Yuan, Ali Bakhoda, Tor M. Aamodt
121
Voted
CLUSTER
2006
IEEE
15 years 8 months ago
Cluster-based IP Router: Implementation and Evaluation
IP routers are now increasingly expected to do more than just traditional packet forwarding – they must be extensible as well as scalable. It is a challenge to design a router a...
Qinghua Ye, Mike H. MacGregor
DAC
1996
ACM
15 years 6 months ago
A Description Language for Design Process Management
A language for defining design discipline characteristics is proesign discipline characteristics such as abstraction levels, design object classifications and decompositions, desi...
Peter R. Sutton, Stephen W. Director
DATE
2004
IEEE
126views Hardware» more  DATE 2004»
15 years 5 months ago
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures
Latency-insensitive systems were recently proposed by Carloni et al. as a correct-by-construction methodology for single-clock system-on-a-chip (SoC) design using predesigned IP b...
Montek Singh, Michael Theobald
EGITALY
2006
15 years 3 months ago
Solutions to 3D Building Reconstruction from Photographs
The 3D model reconstruction of buildings from uncalibrated photographs allows new useful Computer Graphics and Computer Vision applications. In this paper we survey some solutions...
Giovanni Maria Farinella, G. Mattiolo