473 search results - page 16 / 95 » Design Methodologies for Noise in Digital Integrated Circuit... |
116
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ICCAD
2003
IEEE
15 years 8 months ago
2003
IEEE
This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical model for SET is al...
ICCD
2001
IEEE
15 years 8 months ago
2001
IEEE
CMOS Phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. PLLs are very sensitive to noise fluctuations on the power and ground rails. In this paper...
122
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DATE
2010
IEEE
15 years 4 months ago
2010
IEEE
We model and verify analog designs in the presence of noise and process variation using an automated theorem prover, MetiTarski. Due to the statistical nature of noise, we propose ...
102
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GLVLSI
2010
IEEE
15 years 4 months ago
2010
IEEE
A methodology is proposed for designing robust circuits exhibiting higher tolerance to process and environmental variations. This higher tolerance is achieved by exploiting the in...
ICCD
2005
IEEE
15 years 8 months ago
2005
IEEE
As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for VLSI design. This paper,...