473 search results - page 3 / 95 » Design Methodologies for Noise in Digital Integrated Circuit... |
SBCCI
2004
ACM
15 years 2 months ago
2004
ACM
This paper presents a design methodology for RF CMOS Low Noise Amplifiers (LNA). This methodology uses a current–based MOSFET model, which allows a detailed analysis of an LNA f...
GLVLSI
2009
IEEE
15 years 4 months ago
2009
IEEE
Resource based optimization for high performance integrated circuits is presented. The methodology is applied to simultaneous shield and repeater insertion, resulting in minimum c...
ICCAD
1998
IEEE
15 years 1 months ago
1998
IEEE
Noise can cause digital circuits to switch incorrectly and thus produce spurious results. Noise can also have adverse power, timing and reliability e ects. Dynamic logic is partic...
SBCCI
2003
ACM
15 years 2 months ago
2003
ACM
As we scale down to deep submicron (DSM) technology, noise is becoming a metric of equal importance as power, speed, and area. Smaller feature sizes, low voltage, and high frequen...
ICCAD
2001
IEEE
15 years 6 months ago
2001
IEEE
: This paper describes ASF, a novel cell-level analog synthesis framework that can size and bias a given circuit topology subject to a set of performance objectives and a manufactu...