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SLIP
2009
ACM
15 years 6 months ago
Floorplan-based FPGA interconnect power estimation in DSP circuits
A novel high-level approach for estimating power consumption of global interconnects in data-path oriented designs implemented in FPGAs is presented. The methodology is applied to...
Ruzica Jevtic, Carlos Carreras, Vukasin Pejovic
ASPDAC
2012
ACM
290views Hardware» more  ASPDAC 2012»
13 years 7 months ago
CODA: A concurrent online delay measurement architecture for critical paths
With technology scaling, integrated circuits behave more unpredictably due to process variation, environmental changes and aging effects. Various variation-aware and adaptive desi...
Yubin Zhang, Haile Yu, Qiang Xu
GLVLSI
2002
IEEE
106views VLSI» more  GLVLSI 2002»
15 years 4 months ago
A low power direct digital frequency synthesizer with 60 dBc spectral purity
We present a low-power sine-output Direct Digital Frequency Synthesizer (DDFS) realized in 0.18 µm CMOS that achieves 60 dBc spectral purity from DC to the Nyquist frequency. No ...
J. M. Pierre Langlois, Dhamin Al-Khalili
DAC
2006
ACM
16 years 24 days ago
Placement of digital microfluidic biochips using the t-tree formulation
Droplet-based microfluidic biochips have recently gained much attention and are expected to revolutionize the biological laboratory procedure. As biochips are adopted for the comp...
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
DAC
2012
ACM
13 years 2 months ago
Statistical design and optimization for adaptive post-silicon tuning of MEMS filters
Large-scale process variations can significantly limit the practical utility of microelectro-mechanical systems (MEMS) for RF (radio frequency) applications. In this paper we desc...
Fa Wang, Gokce Keskin, Andrew Phelps, Jonathan Rot...