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» Design Principles for Combiners with Memory
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MTDT
1999
IEEE
88views Hardware» more  MTDT 1999»
15 years 1 months ago
Computing in Memory Architectures for Digital Image Processing
Continuing improvements in semiconductor fabrication density are enabling new classes of System-on-aChip architectures that combine extensive processing logic and high-density mem...
Luke Roth, Lee D. Coraor, David L. Landis, Paul T....
DSD
2010
IEEE
162views Hardware» more  DSD 2010»
14 years 8 months ago
A Parallel for Loop Memory Template for a High Level Synthesis Compiler
—We propose a parametrized memory template for applications with parallel for loops. The template’s parameters reflect important trade-offs made during system design. The temp...
Craig Moore, Wim Meeus, Harald Devos, Dirk Strooba...
ISCAS
2003
IEEE
172views Hardware» more  ISCAS 2003»
15 years 2 months ago
Performance modeling of resonant tunneling based RAMs
Tunneling based random-access memories (TRAM’s) have recently garnered a great amount of interests among the memory designers due to their intrinsic merits such as reduced power...
Hui Zhang, Pinaki Mazumder, Li Ding 0002, Kyoungho...
CF
2009
ACM
15 years 4 months ago
Strategies for dynamic memory allocation in hybrid architectures
Hybrid architectures combining the strengths of generalpurpose processors with application-specific hardware accelerators can lead to a significant performance improvement. Our ...
Peter Bertels, Wim Heirman, Dirk Stroobandt
VEE
2009
ACM
107views Virtualization» more  VEE 2009»
15 years 4 months ago
Architectural support for shadow memory in multiprocessors
Runtime monitoring support serves as a foundation for the important tasks of providing security, performing debugging, and improving performance of applications. Often runtime mon...
Vijay Nagarajan, Rajiv Gupta