We present a new technique to examine the trade-off regions of a circuit where its competing performances become “simultaneously optimal”, i.e. Pareto optimal. It is based on ...
An increasing number of distributed applications are being constructed by composing them out of existing applications. The resulting applications can be very complex in structure,...
During the past few years, embedded digital systems have been requested to provide a huge amount of processing power and functionality. A very likely foreseeable step to pursue th...
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
Stencil computations form the performance-critical core of many applications. Tiling and parallelization are two important optimizations to speed up stencil computations. Many til...