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IPPS
2005
IEEE
15 years 3 months ago
Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores
The use of pipelined floating-point arithmetic cores to create high-performance FPGA-based computational kernels has introduced a new class of problems that do not exist when usi...
Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna
ASPDAC
2004
ACM
109views Hardware» more  ASPDAC 2004»
15 years 2 months ago
Resource-constrained low-power bus encoding with crosstalk delay elimination
— In deep-submicron (DSM) technology, minimizing power consumption of a bus is one of the most important design objectives in embedded system-on-chip (SoC) design. In this paper,...
Meeyoung Cha, Chun-Gi Lyuh, Taewhan Kim
FPL
2007
Springer
97views Hardware» more  FPL 2007»
15 years 1 months ago
An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems
Recently, there is a surge of interests in using FPGAs for computer architecture research including applications from emulating and analyzing a new platform to accelerating microa...
Taeweon Suh, Shih-Lien Lu, Hsien-Hsin S. Lee
ISQED
2011
IEEE
240views Hardware» more  ISQED 2011»
14 years 9 days ago
Fast optimization of nano-CMOS mixed-signal circuits through accurate metamodeling
—Design optimization methodologies for AMS-SoCs with analog, digital, and mixed-signal portions have not received significant attention, due to their high complexity. In mixed-s...
Oleg Garitselov, Saraju P. Mohanty, Elias Kougiano...
ISCA
2012
IEEE
218views Hardware» more  ISCA 2012»
12 years 11 months ago
CAPRI: Prediction of compaction-adequacy for handling control-divergence in GPGPU architectures
Wide SIMD-based GPUs have evolved into a promising platform for running general purpose workloads. Current programmable GPUs allow even code with irregular control to execute well...
Minsoo Rhu, Mattan Erez