761 search results - page 9 / 153 » Design and Analysis of a Robust Pipelined Memory System |
ASPDAC
2012
ACM
13 years 5 months ago
2012
ACM
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
HPDC
2003
IEEE
15 years 3 months ago
2003
IEEE
We present a study of six batch-pipelined scientific workloads that are candidates for execution on computational grids. Whereas other studies focus on the behavior of single app...
EMSOFT
2006
Springer
15 years 1 months ago
2006
Springer
Upper bounds on worst-case execution times, which are commonly called WCET, are a prerequisite for validating the temporal correctness of tasks in a real-time system. Due to the e...
IEEEPACT
2003
IEEE
15 years 3 months ago
2003
IEEE
Graphics and media processing is quickly emerging to become one of the key computing workloads. Programmable graphics processors give designers extra flexibility by running a sma...
DAC
2006
ACM
15 years 10 months ago
2006
ACM
The increasing use of Multiprocessor Systems-on-Chip (MPSoCs) for high performance demands of embedded applications results in high power dissipation. The memory subsystem is a la...