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» Design and CAD for 3D integrated circuits
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VLSID
2010
IEEE
190views VLSI» more  VLSID 2010»
14 years 8 months ago
Rethinking Threshold Voltage Assignment in 3D Multicore Designs
Due to the inherent nature of heat flow in 3D integrated circuits, stacked dies exhibit a wide range of thermal characteristics. The strong dependence of leakage with temperature...
Koushik Chakraborty, Sanghamitra Roy
SLIP
2009
ACM
15 years 4 months ago
Integrated interlayer via planning and pin assignment for 3D ICs
As technology advances, 3D ICs are introduced for alleviating the interconnect problem coming with shrinking feature size and increasing integration density. In 3D ICs, one of the...
Xu He, Sheqin Dong, Xianlong Hong, Satoshi Goto
DAC
2010
ACM
15 years 1 months ago
Cost-driven 3D integration with interconnect layers
The ever increasing die area of Chip Multiprocessors (CMPs) affects manufacturing yield, resulting in higher manufacture cost. Meanwhile, network-on-chip (NoC) has emerged as a p...
Xiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna ...
ICCAD
2009
IEEE
94views Hardware» more  ICCAD 2009»
14 years 7 months ago
Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint
We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration. ...
Li Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. ...
ISPD
2011
ACM
253views Hardware» more  ISPD 2011»
14 years 21 days ago
Assembling 2D blocks into 3D chips
Three-dimensional ICs promise to significantly extend the scale of system integration and facilitate new-generation electronics. However, progress in commercial 3D ICs has been s...
Johann Knechtel, Igor L. Markov, Jens Lienig