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COSIT
2005
Springer
106views GIS» more  COSIT 2005»
15 years 5 months ago
Investigating the Need for Eliminatory Constraints in the User Interface of Bicycle Route Planners
According to choice models in economics, consumer choice can be modeled as a two-stage process, starting with the choice of feasible alternatives, called the screening process, fol...
Hartwig H. Hochmair, Claus Rinner
95
Voted
ASPLOS
2008
ACM
15 years 1 months ago
Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industry. Most of the current research thrusts using chip multiprocessors (CMPs) as th...
Chinnakrishnan S. Ballapuram, Ahmad Sharif, Hsien-...
EUROPAR
2009
Springer
15 years 3 months ago
StarPU: A Unified Platform for Task Scheduling on Heterogeneous Multicore Architectures
Abstract. In the field of HPC, the current hardware trend is to design multiprocessor architectures that feature heterogeneous technologies such as specialized coprocessors (e.g., ...
Cédric Augonnet, Samuel Thibault, Raymond N...
ISCA
2005
IEEE
181views Hardware» more  ISCA 2005»
15 years 5 months ago
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishn...
CODES
2007
IEEE
15 years 6 months ago
Event-based re-training of statistical contention models for heterogeneous multiprocessors
Embedded single-chip heterogeneous multiprocessor (SCHM) systems experience frequent system events such as task preemption, power-saving voltage/frequency scaling, or arrival of n...
Alex Bobrek, JoAnn M. Paul, Donald E. Thomas