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» Design and Performance of Optimized Relay Mappings
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CODES
2007
IEEE
15 years 4 months ago
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC
Heterogeneous multiprocessors are emerging as the dominant implementation approach to embedded multiprocessor systems. In addition to having processing elements suited to the targ...
Brett H. Meyer, Donald E. Thomas
ANCS
2005
ACM
15 years 3 months ago
Resource mapping and scheduling for heterogeneous network processor systems
Task to resource mapping problems are encountered during (i) hardware-software co-design and (ii) performance optimization of Network Processor systems. The goal of the first pro...
Liang Yang, Tushar Gohad, Pavel Ghosh, Devesh Sinh...
GLOBECOM
2007
IEEE
15 years 4 months ago
Beamforming with Limited Feedback in Amplify-and-Forward Cooperative Networks
— A relay selection approach has previously been shown to outperform repetition-based scheduling for both amplify-and-forward (AF) and decode-and-forward (DF) cooperative network...
Yi Zhao, Raviraj Adve, Teng Joon Lim
DAC
1993
ACM
15 years 1 months ago
On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping
In this paper we study the area and depth trade-off in LUT based FPGA technology mapping. Starting from a depth-optimal mapping solution, we perform a number of depth relaxation o...
Jason Cong, Yuzheng Ding
ISLPED
2005
ACM
103views Hardware» more  ISLPED 2005»
15 years 3 months ago
A technique for low energy mapping and routing in network-on-chip architectures
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC design with mesh ba...
Krishnan Srinivasan, Karam S. Chatha