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» Design and Performance of Optimized Relay Mappings
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TC
2011
14 years 4 months ago
Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines
—Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Since a large fraction of chip area is devoted to on-...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
GECCO
2008
Springer
174views Optimization» more  GECCO 2008»
14 years 11 months ago
Mask functions for the symbolic modeling of epistasis using genetic programming
The study of common, complex multifactorial diseases in genetic epidemiology is complicated by nonlinearity in the genotype-to-phenotype mapping relationship that is due, in part,...
Ryan J. Urbanowicz, Nate Barney, Bill C. White, Ja...
ICCAD
2004
IEEE
155views Hardware» more  ICCAD 2004»
15 years 6 months ago
A flexibility aware budgeting for hierarchical flow timing closure
—In this paper, we present a new block budgeting algorithm which speeds up timing closure in timing driven hierarchical flows. After a brief description of the addressed flow, ...
Olivier Omedes, Michel Robert, Mohammed Ramdani
IBMSJ
2006
96views more  IBMSJ 2006»
14 years 9 months ago
Running Quake II on a grid
ed underlying grid infrastructure to an application) allowed us to reuse an existing game engine without the need to make any significant changes to it. In this paper we examine th...
Glenn Deen, Matthew Hammer, John Bethencourt, Iris...
DAC
2008
ACM
15 years 10 months ago
Scan chain clustering for test power reduction
An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen...