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» Design and Performance of Optimized Relay Mappings
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MICRO
2009
IEEE
124views Hardware» more  MICRO 2009»
15 years 4 months ago
ZerehCache: armoring cache architectures in high defect density technologies
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
EMSOFT
2006
Springer
15 years 1 months ago
New approach to architectural synthesis: incorporating QoS constraint
Embedded applications like video decoding, video streaming and those in the network domain, typically have a Quality of Service (QoS) requirement which needs to be met. Apart from...
Harsh Dhand, Basant Kumar Dwivedi, M. Balakrishnan
PLDI
2011
ACM
14 years 20 days ago
Automatic compilation of MATLAB programs for synergistic execution on heterogeneous processors
MATLAB is an array language, initially popular for rapid prototyping, but is now being increasingly used to develop production code for numerical and scientific applications. Typ...
Ashwin Prasad, Jayvant Anantpur, R. Govindarajan
VLSID
2002
IEEE
98views VLSI» more  VLSID 2002»
15 years 10 months ago
On Test Scheduling for Core-Based SOCs
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
Sandeep Koranne
AAAI
2006
14 years 11 months ago
Sample-Efficient Evolutionary Function Approximation for Reinforcement Learning
Reinforcement learning problems are commonly tackled with temporal difference methods, which attempt to estimate the agent's optimal value function. In most real-world proble...
Shimon Whiteson, Peter Stone