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» Design and architectures for dependable embedded systems
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GLVLSI
1998
IEEE
122views VLSI» more  GLVLSI 1998»
15 years 4 months ago
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
Luca Benini, Giovanni De Micheli, Alberto Macii, E...
CODES
2000
IEEE
15 years 4 months ago
Frequency interleaving as a codesign scheduling paradigm
Frequency interleaving is introduced as a means of conceptualizing and co-scheduling hardware and software behaviors so that software models with conceptually unbounded state and ...
JoAnn M. Paul, Simon N. Peffers, Donald E. Thomas
RSP
1999
IEEE
160views Control Systems» more  RSP 1999»
15 years 4 months ago
Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping
SDL is currently gaining interest as a system level specification language for HW/SW codesign. Automated synthesis of SDL in hardware so far had problems with its efficiency. The ...
Oliver Bringmann, Wolfgang Rosenstiel, Annette Mut...
IPPS
2006
IEEE
15 years 5 months ago
Battery aware dynamic scheduling for periodic task graphs
Battery lifetime, a primary design constraint for mobile embedded systems, has been shown to depend heavily on the load current profile. This paper explores how scheduling guidel...
V. Rao, N. Navet, G. Singhal, A. Kumar, G. S. Visw...
SIGGRAPH
2010
ACM
15 years 4 months ago
Unstructured video-based rendering: interactive exploration of casually captured videos
We present an algorithm designed for navigating around a performance that was filmed as a “casual” multi-view video collection: real-world footage captured on hand held camer...
Luca Ballan, Gabriel J. Brostow, Jens Puwein, Marc...