620 search results - page 3 / 124 » Design and evaluation of an auto-memoization processor |
ISCA
1997
IEEE
15 years 1 months ago
1997
IEEE
In this paper we evaluate the performance of high bandwidth caches that employ multiple ports, multiple cycle hit times, on-chip DRAM, and a line buffer to find the organization t...
70
Voted
CASES
2005
ACM
14 years 11 months ago
2005
ACM
Due to resource and power constraints, embedded processors often cannot afford dedicated floating-point units. For instance, the IBM PowerPC processor embedded in Xilinx Virtex-...
ERSA
2008
14 years 11 months ago
2008
Coarse-grained dynamically reconfigurable processor arrays (DRPAs) have been received an attention as a flexible and efficient off-loading engine for various types of System-on-Ch...
DFT
2008
IEEE
14 years 11 months ago
2008
IEEE
This paper presents a concurrent error detection technique for the control logic of a modern microprocessor. Our method is based on execution time prediction for each instruction ...
HPCA
1997
IEEE
15 years 1 months ago
1997
IEEE
This paper represents a design study of the datapath for a very long instruction word (VLIW) video signal processor (VSP). VLIW architectures provide high parallelism and excellen...