59 search results - page 3 / 12 » Design for Verification in System-level Models and RTL |
CORR
2007
Springer
13 years 6 months ago
2007
Springer
This paper deals with a common verification methodology and environment for SystemC BCA and RTL models. The aim is to save effort by avoiding the same work done twice by different...
DAC
1996
ACM
13 years 10 months ago
1996
ACM
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
DAC
2007
ACM
14 years 7 months ago
2007
ACM
An effective method for focusing optimization effort on the most important parts of a design is to examine those elements on the critical path. Traditionally, the critical path is...
DAC
2006
ACM
14 years 7 days ago
2006
ACM
Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural ...
AHS
2007
IEEE
13 years 10 months ago
2007
IEEE
In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity...