275 search results - page 11 / 55 » Design for Verification of SystemC Transaction Level Models |
81
Voted
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
In this paper, a novel design space exploration approach is proposed that enables a concurrent optimization of the topology, the process binding, and the communication routing of ...
106
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FDL
2007
IEEE
15 years 4 months ago
2007
IEEE
The system description language SystemC enables to quickly create executable specifications at adequate levbstraction for both hardware/software integration and fast design space...
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
—The need to have Transaction Level models early in the design cycle is becoming more and more important to shorten the development times of complex Systems-on-Chip (SoC). These ...
ASPDAC
2009
ACM
15 years 2 months ago
2009
ACM
— This paper proposes the first automatic approach to simultaneously generate Cycle Accurate and Cycle Count Accurate transaction level bus models. Since TLM (Transaction Level M...
115
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FMCAD
2006
Springer
15 years 1 months ago
2006
Springer
The importance of re-usable Intellectual Properties (IPs) cores is increasing due to the growing complexity of today's system-on-chip and the need for rapid prototyping. In th...