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» Design for Verification of SystemC Transaction Level Models
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JTRES
2010
ACM
14 years 10 months ago
The design of SafeJML, a specification language for SCJ with support for WCET specification
Safety-Critical Java (SCJ) is a dialect of Java that allows programmers to implement safety-critical systems, such as software to control airplanes, medical devices, and nuclear p...
Ghaith Haddad, Faraz Hussain, Gary T. Leavens
PLDI
2009
ACM
15 years 4 months ago
Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory
Multicore designs have emerged as the mainstream design paradigm for the microprocessor industry. Unfortunately, providing multiple cores does not directly translate into performa...
Mojtaba Mehrara, Jeff Hao, Po-Chun Hsu, Scott A. M...
AOSD
2009
ACM
15 years 4 months ago
Modelling hardware verification concerns specified in the e language: an experience report
e is an aspect-oriented hardware verification language that is widely used to verify the design of electronic circuits through the development and execution of testbenches. In rec...
Darren Galpin, Cormac Driver, Siobhán Clark...
EMSOFT
2004
Springer
15 years 1 months ago
Separation of concerns: overhead in modeling and efficient simulation techniques
Separating the description of important aspects of a design such as behavior and architecture, or computation and communication, may yield significant advantages in design time as...
Guang Yang 0004, Alberto L. Sangiovanni-Vincentell...
DAC
1996
ACM
15 years 1 months ago
Use of Sensitivities and Generalized Substrate Models in Mixed-Signal IC Design
A novel methodology for circuit design and automatic layout generation is proposed for a class of mixed-signal circuits in presence of layout parasitics and substrate induced nois...
Paolo Miliozzi, Iasson Vassiliou, Edoardo Charbon,...