275 search results - page 43 / 55 » Design for Verification of SystemC Transaction Level Models |
SEUS
2008
IEEE
15 years 4 months ago
2008
IEEE
Abstract— This paper presents SW synthesis using Embedded System Environment (ESE), a tool set for design of multicore embedded systems. We propose a classification of multicore...
SEW
2006
IEEE
15 years 3 months ago
2006
IEEE
The Mondex Electronic Purse is an outstanding example of industrial scale formal refinement, and was the first verification to achieve ITSEC level E6 certification. A formal a...
CSUR
2006
14 years 9 months ago
2006
resents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. ...
DSRT
2008
IEEE
15 years 4 months ago
2008
IEEE
This paper describes a new property checking approach in order to enhance the diagnosis ability of an electronic embedded system, included in an automotive application. We conside...
EMSOFT
2006
Springer
15 years 1 months ago
2006
Springer
Upper bounds on worst-case execution times, which are commonly called WCET, are a prerequisite for validating the temporal correctness of tasks in a real-time system. Due to the e...