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» Design for Verification of SystemC Transaction Level Models
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GPCE
2008
Springer
14 years 10 months ago
Property models: from incidental algorithms to reusable components
A user interface, such as a dialog, assists a user in synthesising a set of values, typically parameters for a command object. Code for “command parameter synthesis” is usuall...
Jaakko Järvi, Mat Marcus, Sean Parent, John F...
IFIP
2010
Springer
14 years 4 months ago
A Formal Analysis of Authentication in the TPM
The Trusted Platform Module (TPM) is a hardware chip designed to enable computers to achieve a greater level of security than is possible in software alone. To this end, the TPM pr...
Stéphanie Delaune, Steve Kremer, Mark Dermo...
CF
2007
ACM
15 years 1 months ago
Massively parallel processing on a chip
MppSoC is a SIMD architecture composed of a grid of processors and memories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution ...
Philippe Marquet, Simon Duquennoy, Sébastie...
ICCAD
2009
IEEE
121views Hardware» more  ICCAD 2009»
14 years 7 months ago
MOLES: Malicious off-chip leakage enabled by side-channels
Economic incentives have driven the semiconductor industry to separate design from fabrication in recent years. This trend leads to potential vulnerabilities from untrusted circui...
Lang Lin, Wayne Burleson, Christof Paar
IFIP
2001
Springer
15 years 2 months ago
Functional Test Generation using Constraint Logic Programming
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre