275 search results - page 6 / 55 » Design for Verification of SystemC Transaction Level Models |
FDL
2005
IEEE
15 years 3 months ago
2005
IEEE
Verification and validation are key issues for today's SoC design projects. This paper presents the implementation of a SystemC based environment for transaction-based verifi...
IPPS
2003
IEEE
15 years 3 months ago
2003
IEEE
To cope with the increasing demand for higher computational power and flexibility, dynamically reconfigurable blocks become an important part inside a system-on-chip. Several meth...
AHS
2007
IEEE
15 years 1 months ago
2007
IEEE
In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity...
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
Simulation of transaction level models (TLMs) is an established embedded systems design technique. Its use cases include virtual prototyping for early software development, platfo...
101
Voted
DAC
2008
ACM
15 years 10 months ago
2008
ACM
A SystemC simulation kernel consists of a deterministic implementation of the scheduler, whose specification is nondeterministic. To leverage testing of a SystemC TLM design, we f...