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2009
ACM
15 years 4 months ago
A case for integrated processor-cache partitioning in chip multiprocessors
Existing cache partitioning schemes are designed in a manner oblivious to the implicit processor partitioning enforced by the operating system. This paper examines an operating sy...
Shekhar Srikantaiah, Reetuparna Das, Asit K. Mishr...
VLSID
2003
IEEE
183views VLSI» more  VLSID 2003»
15 years 10 months ago
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks
We present an innovative design of an accurate, 2D DCT IDCT processor, which handles scaled and sub-sampled input blocks efficiently. In the IDCT mode, the latency of the processo...
Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van...
VLSID
2009
IEEE
108views VLSI» more  VLSID 2009»
15 years 10 months ago
Metric Based Multi-Timescale Control for Reducing Power in Embedded Systems
Abstract--Digital control for embedded systems often requires low-power, hard real-time computation to satisfy high control-loop bandwidth, low latency, and low-power requirements....
Forrest Brewer, João Pedro Hespanha, Nitin ...
JCP
2008
120views more  JCP 2008»
14 years 9 months ago
Multimedia Resource Replication Strategy for a Pervasive Peer-to-Peer Environment
The computer world is experiencing a paradigm shift towards context-aware pervasive computing, where diverse computer devices communicate with each other through different network ...
Letian Rong
ICMCS
2006
IEEE
120views Multimedia» more  ICMCS 2006»
15 years 3 months ago
Movie-Based Multimedia Matrix Library
The paper describes a library supporting effective programming and design of matrix algorithms and programs. The important feature of proposed library is the visual algorithm repr...
Dmitry A. Vazhenin, Alexander Vazhenin