Sciweavers

1146 search results - page 37 / 230
» Design of a multimedia processor based on metrics computatio...
Sort
View
58
Voted
ASPDAC
2004
ACM
104views Hardware» more  ASPDAC 2004»
15 years 3 months ago
A small-area high-performance 512-point 2-dimensional FFT single-chip processor
: A single-chip 512-point FFT processor is presented. This processor is based on the cached-memory architecture (CMA) with the resource-saving multidatapath radix-23 computation el...
Naoto Miyamoto, Leo Karnan, Kazuyuki Maruo, Koji K...
PPOPP
2006
ACM
15 years 3 months ago
High-performance IPv6 forwarding algorithm for multi-core and multithreaded network processor
IP forwarding is one of the main bottlenecks in Internet backbone routers, as it requires performing the longest-prefix match at 10Gbps speed or higher. IPv6 forwarding further ex...
Xianghui Hu, Xinan Tang, Bei Hua
74
Voted
JSAC
2007
127views more  JSAC 2007»
14 years 9 months ago
Mechanism-based resource allocation for multimedia transmission over spectrum agile wireless networks
— We propose to add a new dimension to existing wireless multimedia systems by enabling autonomous stations to dynamically compete for communication resources through adjustment ...
Ahmad Reza Fattahi, Fangwen Fu, Mihaela van der Sc...
81
Voted
CF
2004
ACM
15 years 3 months ago
A first glance at Kilo-instruction based multiprocessors
The ever increasing gap between processor and memory speed, sometimes referred to as the Memory Wall problem [42], has a very negative impact on performance. This mismatch will be...
Marco Galluzzi, Valentin Puente, Adrián Cri...
CODES
2005
IEEE
15 years 3 months ago
Aggregating processor free time for energy reduction
Even after carefully tuning the memory characteristics to the application properties and the processor speed, during the execution of real applications there are times when the pr...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...