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DAC
2004
ACM
15 years 10 months ago
High level cache simulation for heterogeneous multiprocessors
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Don...
ISCA
2012
IEEE
242views Hardware» more  ISCA 2012»
13 years 2 days ago
Side-channel vulnerability factor: A metric for measuring information leakage
There have been many attacks that exploit side-effects of program execution to expose secret information and many proposed countermeasures to protect against these attacks. Howeve...
John Demme, Robert Martin, Adam Waksman, Simha Set...
ICTCS
2003
Springer
15 years 2 months ago
Cost Constrained Fixed Job Scheduling
In this paper, we study the problem of cost constrained fixed job scheduling (CCFJS). In this problem, there are a number of processors, each of which belongs to one of several cla...
Qiwei Huang, Errol L. Lloyd
IPPS
1999
IEEE
15 years 1 months ago
The Paderborn University BSP (PUB) Library - Design, Implementation and Performance
The Paderborn University BSP (PUB) library is a parallel C library based on the BSP model. The basic library supports buffered and unbuffered asynchronous communication between an...
Olaf Bonorden, Ben H. H. Juurlink, Ingo von Otte, ...
78
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VLSID
2001
IEEE
117views VLSI» more  VLSID 2001»
15 years 10 months ago
Dynamic Voltage Scheduling Using Adaptive Filtering of Workload Traces
Abstract - An adaptive approach for dynamic voltage scheduling on processors is presented based on workload prediction by filtering a trace history. The effects of update frequency...
Amit Sinha, Anantha Chandrakasan